This invention relates generally to a method for fabricating an integrated circuit and more particularly, to a method for fabricating an integrated circuit which provides improved step coverage.
Microelectronic integrated circuits, in particular superconductor integrated circuits, are formed of multiple dielectric layers having multilayer metal interconnects or wires within and between each layer. These wires create high spots, or steps, in the dielectric layers deposited over the wires, requiring subsequent wire layers to cross over the steps. The wires have a tendency to thin and break at the crossover point because of the strains placed on the wire from the step. These strains are increased with each successively applied dielectric and wire layer. This problem, known as poor step coverage, reduces integrated circuit yield and limits the amount of circuitry which can be included in an integrated circuit by restricting the number of available wiring layers to about four in superconductor integrated circuits. In other integrated circuit technologies, such as CMOS, the surface topology is more severe which limits the number of metal wiring layers to two or possibly three layers.
One method known in the art to reduce the steps and thereby improve step coverage in some integrated circuits is to chemically machine away the steps such that the wires do not cross over steps. However, chemical machining is expensive and time consuming.
Another method known in the art to reduce the steps in some integrated circuits is to apply a high molecular weight polystyrene material and different types of photoresist material over the steps and etch the materials away in a manner such that the steps are etched away. However, this method removes the material unevenly such that the surface of the integrated circuit is only 45-50% planar, which is inadequate for many microelectronic integrated circuit applications.
What is needed therefore, is a method to reduce the steps in an integrated circuit thereby improving step coverage in integrated circuits. The method should provide an integrated circuit having a substantially planar surface free of chemical machining.
The aforementioned need in the prior art is satisfied by this invention, which provides a method for fabricating an integrated circuit having a substrate with a first dielectric material layer. The method comprising the steps of applying a first conductive layer to the first dielectric material layer such that the first conductive layer covers a portion of the first dielectric material layer and extends outwardly therefrom. A portion of the first conductive layer is removed to create a first conductive pattern. A second dielectric layer is deposited over the first conductive pattern and exposed portion of the first dielectric material layer forming steps in said first dielectric material layer. A planarizing material layer is applied over the second dielectric material layer such that the planarizing material layer provides an approximately planar top surface distal from the second dielectric material layer. Portions of the planarizing material layer and the second dielectric material layer are removed such that the approximately planar top surface is approximately continually maintained until the first wire pattern is exposed.